1. Field of Invention
The present invention relates to a wafer level package structure, and more particularly, to a wafer level package structure with an area bump.
2. Description of Related Art
The flip chip interconnect technology mainly disposes a plurality of bonding pads (also known as die pads) on an active surface of a chip (also known as a die) by using an area array layout method, and forms a bump on each bonding pad. After the chip is flipped, the bumps on the bonding pads of the chip are respectively electrically and mechanically connected to the contact pads, which correspond to the surface of a substrate or a Printed Circuit Board (PCB). Further, the flip chip interconnect technology also forms the bumps on the contact pads of the surface of the substrate or the PCB first, and electrically and mechanically connected to their corresponding bumps via the bonding pads on the active surface of the chip, respectively. It needs to be noted that since the flip chip interconnect technology can be applied in the high pin count chip package structure and is advantageous in reducing the package area and shorten the signal transmission path, the flip chip interconnect technology has been widely applied in the chip package field currently. The most common used chip package structures applying the flip chip interconnect technology comprise the chip package structures, such as the Flip Chip Ball Grid Array (FC/BGA) and the Flip Chip Pin Grid Array (FC/PGA).
Referring to both FIG. 1 and FIG. 2, FIG. 1 schematically shows a top view of a conventional flip chip package structure, and FIG. 2 schematically shows a sectional view cut from the I-I line in FIG. 1. The flip chip package structure 100 comprises a substrate 110, a chip 130, and a plurality of bumps 140. As shown in FIG. 2, the substrate 110 comprises a substrate surface 112 and a plurality of contact pads 114, wherein the contact pads 114 are disposed on the substrate surface 112 of the substrate 110. Further, the chip 130 comprises an active surface 132, wherein the active surface 132 of the chip 130 roughly means the surface on which the active devices (not shown) are disposed. The chip 130 further comprises a plurality of bonding pads 134, which disposed on the active surface 132 of the chip 130 and used as a media for input/output the signal of chip 130. The contact pads 114 are correspondingly disposed on the bonding pads 134, respectively. Further, the bumps 140 electrically and mechanically connect one of the bonding pads 134 to one of its corresponding contact pads 114, respectively. Finally, an underfill 150 is filled into the cavity surrounded by the substrate 110, the chip 130, and the bumps 140, so as to protect the exposed portion of the contact pads 114, the bonding pads 134, and the bumps 140.
Regarding to the conventional flip chip interconnect technology, the bonding pads of the chip, which provide the functions of signal, power and ground, are electrically and mechanically connected to their corresponding contact pads of the substrate via the same size ball bumps, respectively. It needs to be noted that the electrical performance and the heat dissipation performance are constant for the same size bumps, thus it is hardly achieved the object of improving the electrical performance and the heat dissipation performance by using the same size bumps after the chip is packaged. Therefore, if the designer intends to significantly improve the electrical performance and the heat dissipation performance after the chip is packaged, a new structure has to be developed.